This invention relates to a semiconductor device adapted for use in mobile communication devices using a microwave band ranging from 800 MHz to 2.5 GHz, such as cellular phone systems, and more particularly, to a technique effective for application to an amplifier element of a high frequency power amplifier outputting high frequency signals after amplification of power.
In recent years, mobile communication devices, or so-called portable telephones, typical of which are communication systems including a GSM (Global System for Mobile Communication) system, a PCS (Personal Communication Systems), a PDC (Personal Digital Cellular) system, a W-CDMA (Code Division Multiple Access) system and the like, have rapidly, globally been in wide use. It has thus become important how the high performance, miniaturization and high reliability of base station systems therefor are realized. The arrangements of these mobile communication station systems are, for example, set out in xe2x80x9cNEC Technical Reportxe2x80x9d vol. 51, No. 7 (1998), pp. 9-15.
One of main constituting components of the base station system includes a high frequency power amplifier for transmitting high frequency signals to an antenna. The amplification element used in the amplifier is made of a bipolar transistor and an insulated gate type field effect transistor (hereinafter referred to simply as MOSFET), each using a silicon (Si) substrate, and a transistor using a compound semiconductor substrate, typical of which is GaAs. Especially, the MOSFET using a silicon substrate is now predominantly employed as the amplification element because of its advantages that a high breakdown voltage is so easy that high power can be conveniently established, that MOSFET is thermally stable and is thus highly reliable, and that a circuit arrangement becomes simple because of the drive by voltage.
As for the MOSFET for the amplification element, a first prior art technique is known as set out, for example, in IEDM Technical Digest. 1996, pp. 87-90 and Microwave Workshop and Exhibition (MWE) Digest, 1999, pp. 289-294. The MOSFET set forth in these references has such an LDMOS (Lateral Diffusion MOS) structure, in which a p-type impurity is diffused from a source side of a gate electrode, for the purposes of preventing punch-through and controlling a threshold voltage, and is provided with an offset structure between the gate electrode and the drain electrode for ensuring a high breakdown voltage. In addition, a source electrode is formed so as to cover the gate electrode therewith, thereby reducing the capacitance between the gate electrode and the drain electrode (Cgd: feedback capacitance). This is called Faraday-shield.
In the above prior art technique, in order to obtain high output power of 100 W or over, MOSFET is so arranged that gate length=0.6 xcexcm, gate oxide film thickness=40 nm and gate width=approximately 100 to 400 nm. With the MOSFET having such a size as mentioned above, the input and output capacitances range from several tens to several hundreds of pF, so that input and output impedances at a working frequency of 2 GHz is as small as approximately 1xcexa9. When the MOSFET in this state is assembled in a package and an attempt is made to impedance conversion to 50xcexa9 at an external matching circuit, the conversion ratio is so great as to lead to a loss at a transmission line and a band reduction. Accordingly, the impedance is improved by arranging the matching circuit from a MOS capacitance chip inside a package located as closely to FET as possible and an inductance depending on a wire.
With respect to a further improvement in performance of MOSFET for the amplification element, a second prior art technique is known as set out in U.S. Pat. No. 5,918,137 of Ng et al. In this prior art technique, in order to improve the high frequency performance and reliability of MOSFET, a shield conductive film made of the same type of material as used for a gate electrode is formed on an insulating film between the gate electrode and the drain electrode.
At least a part of the insulating film and the shield conductive film are, respectively, formed according to the same step as a gate insulating film and the gate electrode of the MOSFET, thus being not complicated in process. Because the gate electrode and the shield conductive film are self-alignedly arranged, the variation of electric characteristics can be suppressed. This MOSFET structure ensures the reduction in capacitance between the gate electrode and the drain electrode (Cgd) when the shield conductive film is set at the same potential as a source, enabling one to improve the power gain in high frequency operations. In addition, the electric field in the substrate surface at the end of the gate electrode can be limited, making it possible to improve a drain breakdown voltage and suppress characteristic degradation ascribed to hot electron injection.
According to our investigations, the first and second prior art techniques have the following problems, respectively.
The MOSFET structure in the first prior art technique has the source electrode, with which the gate electrode is covered, formed on a thick interlayer insulating film, so that the portion between the side wall of the gate electrode and the drain electrode cannot be shielded and the effect of limiting the electric field against the substrate is small. Thus, satisfactory effects on the reduction in capacitance between the gate electrode and the drain electrode (Cgd), the improvement in drain breakdown voltage and the suppression of degradation caused by hot electrons cannot be obtained.
Although the MOSFET structure in the second prior art technique takes into account the reduction in electrostatic capacitance (Cgd) between the gate electrode and a drain semiconductor region (or drain electrode), capacitances between other wirings are not taken into consideration. More particularly, the shield conductive film and the gate electrode are formed in the same step, under which the thickness of the shield conductive film is determined depending on the requirement for the gate electrode, so that the capacitance (Cgs) between the shield conductive film and the side wall of the gate electrode cannot be freely made small.
Likewise, with respect to the capacitance between the drain electrode and the shield conductive film (Cds) determined on the thickness of the shield conductive film, the drain electrode is made thicker than the shield conductive film because of the necessity in current capacity. Accordingly, it is not possible to reduce the capacitance by freely decreasing the thickness of the shield conductive film. Moreover, the thickness of the insulating film provided beneath the shield conductive film is thin, like the gate insulating film, so that the electrostatic capacitance between the shield conductive film and the drain-offset semiconductor region appears to be great, thereby increasing the capacitance between the drain and the source. Additionally, when using a structure provided with a gate shunt wiring on the gate electrode for the purpose of reducing the gate resistance, an electrostatic capacitance is established between the shield conductive film and the gate shunt wiring, with the result that the capacitance between the gate electrode and the source increases over the case where no shield conductive film exists.
All the capacitances stated hereinabove are added to the input and output capacitances (Cgs, Cds) of the MOSFET. These lower the input and output impedances of the MOSFET in high frequency operations, so that if a matching circuit is provided in a package, a loss in the matching circuit becomes significant, with the attendant problem that output power and an efficiency are lowered. Moreover, the conversion ratio of the impedance becomes great, thus being inconvenient from the standpoint of design margins such as of a frequency band and a packaging area. The increase of the input capacitance (Cgs) has the problem that the frequency cut-off of a MOS transistor is lowered and the high frequency power gain is lowered.
On the other hand, where the gate shunt wiring is not used by arranging the gate electrode that has a double structure (or a polyside structure) of polysilicon and tungsten silicide to reduce the resistance, the parasitic capacitance between the gate electrode and the shield conductive film can be reduced, but the resistance of the gate electrode is not appreciably small, so that limitation is placed on the width (i.e. a finger width) of the gate electrode. Thus, there arises the problem that the freedom of a layout of MOSFET is lost, thereby increasing the parasitic resistance or capacitance.
An object of the invention is to provide a semiconductor device wherein the increase in input and output capacitances of MOSFET is minimized, and the feedback capacitance ascribed to a shield conductive film is reduced, a drain breakdown voltage and a current capacitance are improved through limitation of an electric field and hot-electron degradation can be suppressed without increasing a loss at an impedance matching circuit.
Another object of the invention is to provide a semiconductor device wherein the resistance of a gate electrode of MOSFET can be reduced to a full extent and the effect of a shield conductive film is brought about thereby ensuring both an improvement in output power and efficiency in high frequency, great power operations and reliability.
The above and other objects and novel features of the invention will become apparent from the description of the specification with reference to the accompanying drawings.
Typical embodiments of the invention are briefly described below.
The MOSFET of the invention comprises a gate electrode formed over a gate insulating film, a source semiconductor region, a drain semiconductor region kept away from the gate electrode, a drain-offset semiconductor region formed between the gate electrode and the drain semiconductor region, and a shield conductive film formed over the drain-offset semiconductor region and electrically connected to the source semiconductor region, wherein the shield conductive film has a thickness smaller than the gate electrode.
Preferably, the MOSFET of the invention further comprises a gate insulating film and a first insulating film provide between the drain-offset semiconductor region and the shield conductive film formed thereover.
Preferably, the MOSFET of the invention is arranged such that in at least a portion of a planar layout thereof, the drain electrode, the shield conductive film, the gate electrode, the source electrode and the gate shunt wiring are arranged in this order. Moreover, these portions extend in parallel to one another.
The provision of the shield conductive film between the gate electrode and the drain electrode of the MOSFET acts to reduce the capacitance between the gate electrode and the drain-offset semiconductor region and also to limit the electric field in the drain region (the region including the drain-offset) at the end portion of the gate electrode.
To arrange the shield conductive film not to be superposed with the gate electrode in a planar pattern and to make the thickness of the shield conductive film smaller than that of the gate electrode serve to suppress an increase in capacitance between the electrodes to a minimum by arranging the shield conductive film.
Moreover, to make the thickness of the insulating film beneath the shield conductive film smaller than that of the gate insulating film acts to suppress the capacitance between the shield conductive film and the drain-offset semiconductor region to a minimum.
The shunt of the gate electrode with a wiring (i.e. a gate shunt wiring) acts to suppress the lowering of a power gain in a high-frequency wave by reduction of the gate resistance.